1. Field of Invention
The present invention relates to a semiconductor integrated circuit (“driver IC”) to drive an image display apparatus, such as a liquid crystal panel.
2. Description of Related Art
FIG. 5 is a schematic that shows a related art driver IC to drive a liquid crystal panel. In FIG. 5, a plurality of output terminals of a segment driver 102 to output display signals S0 to S15 are connected, via a wiring pattern formed on a substrate 100, to a plurality of electrodes that are aligned in the segment direction on a liquid crystal panel 104. A plurality of output terminals of a common driver 101 to output the scanning signals C0 to C15 are also connected via a wiring pattern formed on the substrate 100 to a plurality of electrodes that are aligned in the common direction on the liquid crystal panel 104.
The common driver 101 and the segment driver 102 are connected to an MPU (Micro Processing Unit) 105. A RAM (Random Access Memory) 103 that is connected to the MPU 105 temporarily stores image data. The MPU 105 generates the display signals S0 to S15 based on the image data stored in the RAM 103 and supplies such signals to the segment driver 102. Based on these signals, the segment driver 102 simultaneously supplies the display signals S0 to S15 to the plurality of electrodes that are aligned in the segment direction on the liquid crystal panel 104. The MPU 105 also generates the scanning signals C0 to C15 based on the image data stored in the RAM 103 and supplies such signals to the common driver 101. Based on these signals, the common driver 101 successively supplies the scanning signals C0 to C15 to the plurality of electrodes that are aligned in the common direction on the liquid crystal panel 104 and so scans the liquid crystal panel 104.
In the related art, separate dedicated ICs are used as the segment driver and the common driver. However, in order to reduce the number of types of ICs, it would be conceivably possible to use the same type of IC commonly used as the segment driver and the common driver.
FIG. 6 is a schematic that shows a driver IC that can be used as either of the segment driver and the common driver. As shown in FIG. 6, this driver IC includes latch circuits 106 that latch display data that is inputted from the MPU via a display data bus, data I/O control circuits 107 and 108 that input or output scanning data that has been generated by the MPU, switches 109 and 110 that switch the driver IC between being operated as a segment driver and being operated as a common driver, switches 111 and 112 that switch the scanning direction during operating the driver IC as a common driver, and a first to Nth DFFs (Delay Flip Flops) 113 that hold data in synchronization with an LP (line pulse) signal.
When operating the driver IC as a segment driver (hereinafter “segment mode”), the SC signal is always at a high level so that the switches 109 are always on state and the SC bar signal is always at a low level, so that the switches 110 are always in an off state. This means that the first to Nth DFFs 113 hold the display data latched by the latch circuit 106 in synchronization with the LP signal, so that the held display data is simultaneously supplied to the output terminals O1 to ON.
On the other hand, when operating the driver IC as a common driver (hereinafter “common mode”), the SC signal is always at the low level so that the switches 109 are always in an off state and the SC bar signal is always at the high level, so that the switches 110 are always in an on state. In the common mode, it is also possible to switch the scanning direction by disposing the driver IC on the left side of the liquid crystal panel or on the right side of the liquid crystal panel. In a case where the scanning data supplied to the data I/O control circuit 107 is outputted from the data I/O control circuit 107 and returned to the data I/O control circuit 108, the SHL signal is at the high level, so that the switches 111 are turned on and the SHL bar signal is at the low level, so that the switches 112 are turned off. This means that in synchronization with a pulse of the LP signal, the first DFF 113 holds the scanning data outputted by the data I/O control circuit 107 and outputs the held scanning data to the output terminal O1 and the second DFF 113. In synchronization with the next pulse of the LP signal, the second DFF 113 holds the scanning data outputted by the first DFF 113 and outputs the held scanning data to the output terminal O2 and the next DFF 113. By repeating this operation, the scanning data is successively outputted to the output terminals O1 to ON.
Also, in the common mode, in a case where the scanning data supplied to the data I/O control circuit 108 is outputted from the data I/O control circuit 108 and returned to the data I/O control circuit 107, the SHL signal is at the low level so that the switches 111 are turned off and the SHL bar signal is at the high level, so that the switches 112 are turned on. This means that the Nth DFF 113 holds the scanning data outputted by the data I/O control circuit 108 in synchronization with a pulse of the LP signal and outputs the held scanning data to the output terminal ON and the (N−1)th DFF 113. The (N−1)th DFF 113 holds the scanning data outputted by the Nth DFF 113 in synchronization with the next pulse of the LP signal and outputs the held scanning data to the output terminal ON−1 and the next DFF 113. By repeating this operation, the scanning data is successively outputted to the output terminals ON to O1.
In this way, it is possible to design a driver IC that can be used as either a segment driver or a common driver. However, since there is a long distance between the output terminals O1 to ON, there has been the problem that it is necessary to use two long wiring routes for inputting and outputting the scanning data between the data I/O control circuit 107 and the first DFF 113 and between the Nth DFF 113 and the data I/O control circuit 108.